1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices and, more particularly, to highly integrated MOS random-access memory devices having an array of rows and columns of memory cells each having a data storage capacitive element and a transfer-gate MOS transistor.
2. Description of the Related Art
With the increasing needs for high performance and reliability of digital computer systems, MOS random-access memory (RAM) devices are becoming more widely used in the manufacture of digital equipment as the speed and cost advantages of these devices increase. As the number of bits increases, the cell size decreases, the magnitude of the storage capacitor in each cell decreases to reduce the amount of charge carriers that can be stored in each cell. Such reduction in storage carrier amount may lead to the occurrence of an erroneous data accessing operation, causing the reliability to decrease. There is a trade-off between the higher packing density and the reliability: making the cell size smaller can improve the integration density; but making it too small can also degrade the reliability.
A "trench" type dynamic RAM (DRAM) has been proposed to break through the trade-off problem. The basic structure of such trench-type DRAM is shown, for example, in IEDM Tech. Dig., "A Trench Transistor Cross-Point DRAM Cell," by W. F. Richardson et al., 1985 at pp. 714-717. A groove called the "trench" is formed in a semiconductive substrate at each of the cross points between the word lines and the bit lines being transverse to each other on the substrate. A capacitor and a MOS transistor are stacked in the trench. With such a trench cell structure, the data storage capacity may be increased in each cell while attaining an increased packing density.
However, the conventional trench-type DRAM cannot follow the recent high-integration requirement that is becoming strict more and more in the industry of semiconductor devices. As the packing density further increases, the distance between adjacent ones of the cell trenches decreases, causing the probability of occurrence of an undesirable "punch-through" phenomenon to increase between the adjacent trench cells. This may degrade the reliability. More specifically, as typically shown in FIG. 6 of the IEDM reference, each trench is provided with an impurity-doped semiconductive layer acting as an active region of a corresponding MOS transistor. The impurity-doped layer is opposite in conductivity type to the substrate, and is formed to surround the inner wall surface of the trench at a predetermined depth in the substrate. As the distance between adjacent trench cells decreases to increase the packing density, the impurity-doped layer of a certain trench cell becomes nearer in position to that of adjacent trench. This may cause a leak current to flow more easily between adjacent trench cells due to the occurrence of a punch-through phenomenon, which will lead to a degradation in the reliability of the trench-cell type DRAM.
A specific type DRAM has also been proposed to improve the packing density, wherein a cell unit consists of a plurality of one-capacitor/one-transistor cells that are series-connected at a single contact node to a corresponding one of parallel bit lines on a semiconductive substrate. The cell unit having the series-connected cells is ordinarily called the "NAND cell" section. With such NAND-cell type DRAM, the contact nodes for coupling the cells to the bit lines can be reduced in number, causing the packing density to increase.
The NAND-cell type DRAM, however, suffers from the reduction in the data-storage capacity in each cell: as the cell capacitor decreases in area, the carrier storage amount decreases, with the result in the reliability being degraded. Such miniaturization of cell structure also leads to the difficulty in the manufacture of NAND-cell DRAMs at a desired production yield.